As advanced semiconductor technologies continuing to evolve, defect detection and classification have experienced increased challenges because the complex process involved with greatly increased transistor density resulting in high defect rates. This makes it more challenging than before for traditional analysis done by human experts prone to error due to long hours of focus required. Software with rules may be used to overcome this, but still faces the issue to construct them, since image quality varies from process to process and layer to layer. In this paper we propose using a machine learning (ML) model, YOLO (You Only Look Once) v8, that will learn complex rules that can generalize to various image qualities and accurately detect defects without human intervention.
Performing accurate and timely Scanning Electron Microscope (SEM) image analysis to identify wafer defects is crucial as it directly impacts manufacturing yield. In this paper, a machine learning (ML) based approach for analyzing SEM images (from wafer inspection machines) to locate and classify wafer defects is proposed. A state-of-the-art one-stage objection detection model called YOLOv8 (You Only Look Once version 8) is used as it offers a good balance between accuracy and inference speed. Experimental results confirm that an ensemble model composed of multiple YOLOv8 models can predict 6 types of defects with a mean Average Precision (mAP) of 0.789 (at IoU=0.5) for unseen test data consisting of real-world SEM images from 5 wafer fabs that have varying image qualities.
KEYWORDS: Advanced process control, Vacuum chambers, Chemical vapor deposition, Manufacturing, Control systems, Film thickness, Data modeling, Metrology, Simulations, Machine learning
The semiconductor foundry industry struggles with challenges in high-product-mix manufacturing, necessitating enhanced flexibility to address diverse customer demands. Coordinating multiple chambers and process steps with varying designs and technology nodes poses complexities leading to reduced yields and increased costs. The chemical vapor deposition (CVD) process introduces thickness variations due to device layout design and chamber condition drift, impacting transistor parameters and yield. Managing chamber-by-chamber variations is critical for high-volume manufacturing, yet traditional solutions fall short in fab line management, resulting in throughput loss. Conventional VM relies on data from the process chamber, referred to as fault detection and classification (FDC), to predict metrology results. In this study, the extraction of design features for better predictive purposes across diverse layouts and technologies are highlighted. Siemens' Calibre® software is employed for design feature extraction, and machine learning (ML) methodologies to construct the extended VM model. An advanced process control (APC) system using the extended VM model for run-to-run (R2R) control is proposed. It incorporates design features, FDC, and measurements to achieve the desired thickness target. The system triggers updates to the extended VM model based on prediction errors. Through control simulations, the APC system significantly enhances process capability and reduces film thickness variations, confirming its effectiveness in a high-mix product foundry fab. Responding to the growing demand for custom-designed products, this paper suggests integrating an ML-based extended VM model with design features and FDC into the APC system, presenting a promise solution for high-product-mix manufacturing.
Modern semiconductor fabrication pushes the limits of chemistry and physics while simultaneously employing largescale, cutting-edge processing techniques. While fab expansion and capital expenditures continue to grow, the human element has become ever more demanding and prone to error. To assist with this issue, computer-aided process engineering, process control, and tool monitoring will continue to rise in the coming years. In this paper, we present an APC-integrated, customizable solution to an in-fab processing segment. Through machine learning, we combine information from design-specific extracted features with processing and metrology data to predict oxide deposition thickness. The result is a design-aware augmentation for current metrology that can recommend accurate process recipe conditions for new layouts. We also present experimental results highlighting the benefits of adding design-aware features with in-fab data to anchor and support each other across layouts and technologies. This result paves the way to decouple, isolate, and quantify the individual influences each processing step imposes on different designs at various stages of the fabrication flow.
Automotive semiconductor products demand high reliability. The current process of performing electrical test after fab-out may not be sufficient for efficient reliability management. This paper proposes an AI solution for improving the reliability of automotive semiconductor products. The solution includes two unique concepts: fab-data augmentation (FDA) to estimate missing values using partially available measurement data during the fabrication process and real-time prediction of reliability using machine learning (ML) models. The ML model is also used to identify and rank critical process steps that impact reliability, and to predict the reliability of wafers in real time. This allows low reliability wafers to be screened out early during the chip fabrication process, improving the overall reliability of the final product.
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