We are developing a 1x8 single mode (SM) optical interface to facilitate the adoption of dense wavelength division multiplexing (DWDM) silicon photonic (SiPh) optical interconnects in exascale computing systems. A common method for fiber attachment to SiPh transceivers is ‘pigtailing’- the permanent adhesive bonding of fiber/v-groove arrays to onchip grating couplers (GC). This approach precludes standard high throughput surface mounting and solder reflow assembly of the transceiver onto system printed circuit boards. Our approach replaces the fixed pigtail with a low profile, small form factor, detachable expanded beam optical connector which consists of four essential parts: a GC array, a surface mount glass microlens array chip, an injection molded solder reflowable optical socket, and an injection molded SM light turn ferrule. The optical socket and ferrule are supplied by US Conec Ltd. To design the GC, we developed an optical simulator that considers CMOS foundry constraints in the optimization process. On-wafer measurements of the GC coupling loss to SMF28 fiber at 1310nm is ~1.4dB with a 1dB bandwidth of ~22nm. This ensures a wide low loss spectral window for at least 16 DWDM channels. The geometry of the optical system is arranged so that only a simple spherical lens is required for efficient mode matching in the expanded beam space. The fiber to fiber insertion loss through the light turn ferrule, two microlenses and GCs, and a looped back SOI waveguide ranged from 4.1-6.3dB, with insertion loss repeatability of 0.2dB after multiple mating cycles.
The need for additional IO bandwidth for data center device interconnection is well established. Optical interconnects can deliver required bandwidth along with energy and space efficiency at a cost that encourages adoption. To this end, we are developing an optical transceiver incorporating multimode VCSEL emitters in a coarse wavelength division multiplex (CWDM) system capable of transmission at 25Gbps per channel, 100Gbps/fiber, and a maximum aggregate bidirectional data rate of 1.2Tbps. Electrical connection to the transceiver can be made by solder reflow or LGA connector, and optical connection is made by means of a custom optical connector supporting CWDM transmission.
In this paper we report on a holographic method used to record fast events in the nanosecond time scale. Several frames of the expansion of shock waves in air and in a polymer sample are recorded holographically in a single shot experiment, using a pulse train generated with a single pulse from a Q-switched Nd:YAG laser. The time resolution is limited by the laser pulse width, which is 5.9 ns. The different frames are recorded on the holographic material using angle multiplexing. Two cavities are used to generate the signal and reference pulses at different angles. We also present a method in which the recording material is replaced by a CCD camera. In this method the holograms are recorded directly on the CCD and digitally reconstructed. The holograms are recorded on a single frame of the CCD camera and then digitally separated and reconstructed.
The Optically Programmable Gate Array (OPGA), an optical version of a conventional FPGA, benefits from a direct parallel interface between an optical memory and a logic circuit. The OPGA utilizes a holographic memory accessed by an array of VCSELs to program its logic. An active pixel sensor array incorporated into the OPGA chip makes it possible to optically address the logic in a very short time allowing for rapid dynamic reconfiguration. Combining spatial and shift multiplexing to store the configuration pages in the memory, the OPGA module can be made compact. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and database search.
The high data transfer rate achievable in page-oriented optical memories demands for parallel interfaces to logic circuits able to process efficiently the data. The Optically Programmable Gate Array, an enhanced version of a conventional FPGA, utilizes a holographic memory accessed by an array of VCSELs to program its logic. Combining spatial and shift multiplexing to store the configuration pages in the memory, the OPGA module is very compact and has extremely short configuration time allowing for dynamic reconfiguration. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and digit classification.
Reconfigurable processors bring a new computational paradigm where the processor modifies its structure to suit a given application, rather than having to modify the application to fit the device. The Optically Programmable Gate Array, an enhanced version of a conventional FPGA, utilizes a holographic memory accessed by an array of VCSELs to program its logic. Combining spatial and shift multipexing to store the configuration pages in the memory, the OPGA module is very compact and has extremely short configuration time allowing for dynamic reconfiguration. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and digit classification.
We have experimentally discovered that the Signal-to-Noise Ratio (SNR) of holograms initially remains constant as the number of holograms stored increases and drops significantly only after a large number of holograms are recorded. This suggests that in a large-scale memory, the limiting noise source is not crosstalk between holograms but holographic noise due to the prolonged exposure of the signal beam. We have carried out experiments to investigate the formation and influence of the inter-pixel grating noise and shown that it is a very important form of holographic noise. We also proposed and demonstrated the use of random-phase modulation in the signal to suppress the inter-pixel grating noise.
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