A new modeling technique to accurately represent the mask and wafer process behavior is presented.
The lithography simulation can be done in three steps: i) mask simulation, ii) latent image calculations and iii) resist
process simulation. The leading edge designs, such as 32 nm and beyond, require higher-fidelity models to adequately
represent each of these actual processes. Effects previously considered secondary, have become more pronounced with
each new technology node.
In this approach, we utilized separate physical models for both mask and wafer processes. We demonstrate that the
residual errors can be further reduced when nonlinear mappers are used in addition. The advantage of the presented
approach compared to standard curve-fitting or statistics-based models is its predictive power and adaptive nature.
The physical model parameters were calibrated by a genetic algorithm whose details were outlined in [1]. The nonlinear
mapper model parameters were identified by a gradient descent method.
Given the computational requirements for a practical solution, our approach uses graphics processors as well as CPUs as
computation hardware.
An inverse lithography solution based on optimization is presented. The optimization approach, in effect, operates as an
inverse lithography tool, based on modeling and simulation of the manufacturing process. Given the associated
computational requirements, the proposed solution intentionally uses graphic processors (GPUs) as well as CPUs as computation hardware. Due to the approach we employed, the results are optimized towards manufacturability and process window maximization.
A computational lithography solution addressing accuracy, speed and affordability requirements is presented. In
particular, the cost of computational hardware should be affordable and that the speed and accuracy of the algorithm
should be sufficient to complete a full-chip computation overnight. Given the issues associated with present tools, the
presented solution uses graphic processors (GPUs) as well as CPUs as computation hardware to achieve a breakthrough improvement in speed and affordability. Scalability to large scale clusters has been addressed so that the solution can be simultaneously used by chip designers as well as manufacturers to provide consistency.
A simultaneous optimization of source and mask with full-chip capability is presented. To provide full-chip processing
capability, the solution is intentionally based on GPUs as well as CPUs and made scalable to large clusters while
maintaining convergence. The approach uses a proprietary search algorithm to converge to an optimal solution in the
sense of print quality maximization while obeying existing mask manufacturing, lithography equipment and process
technology constraints. The solution is based on a proprietary optimization function that is applicable to both binary and
phase shift masks.
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