Dr. Jonathan Ho Profile

Dr. Jonathan Ho

Sr. Program Manager at Advanced Micro Devices Inc

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Publications (10)

Proceedings Article | 10 April 2024 Presentation + Paper

An artificial intelligence machine learning (AI/ML) approach with cross-technology node learning for multi-layer process defect predictions

Jonathan Ho, Xiaoyuan Qi, Fan Jiang, Yuyang Sun, Le Hong

Proceedings Volume 12954, 129540F (2024) https://doi.org/10.1117/12.3011296

KEYWORDS: Machine learning, Design, Metals, Data modeling, Artificial intelligence, Engineering, Semiconductors, Image classification, Design rules

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Proceedings Article | 13 March 2009 Paper

Test structures for 40 nm design rule evaluation

Jonathan Ho, Yan Wang, Benjamin Lin

Proceedings Volume 7275, 72750T (2009) https://doi.org/10.1117/12.813448

KEYWORDS: Critical dimension metrology, Transistors, Lithography, Immersion lithography, Diffusion, Lens design, Design for manufacturability, Field programmable gate arrays, Design for manufacturing

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Proceedings Article | 4 March 2008 Paper

A procedure to back-annotate process induced layout dimension changes into the post layout simulation netlist

Jonathan Ho, Yan Wang, Xin Wu, Jane Soward, Ping Zhang, Joanne Wu

Proceedings Volume 6925, 69250V (2008) https://doi.org/10.1117/12.771427

KEYWORDS: Transistors, Diffusion, Optical proximity correction, Lithography, Semiconducting wafers, Oscillators, Etching, Standards development, Model-based design, Scanning electron microscopy

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As transistor dimensions become smaller, on-wafer transistor dimension variations, induced by lithography or etching process, impact more to the transistor parameters than those from the earlier process technologies such as 90 nm and 130 nm. The on-wafer transistor dimension variations are layout dependent and are ignored in the standard post layout verification flow where the transistor parameters in a spice netlist are extracted from drawn transistor dimensions. There are commercial software tools for predicting the on-wafer transistor dimensions for the improved accuracy of the post-layout verification. These tools need accurate models for the on-wafer transistor dimension prediction and the models need to be re-calibrated as the fabrication process is changed. Furthermore, the model-based predictions of the on-wafer transistor dimensions require extensive computing power which can be time consuming. In the paper, a procedure to back-annotate the process induced transistor dimension changes into the post layout extracted netlist using a simple look-up table is described. The lookup table is composed of specified drawn transistor and its sounding layout as well as their on-wafer dimensions. The on-wafer dimensions can be extracted from simulations, SEM in-line pictures or electrical data of specially designed testkeys. Taking the lookup table data, accordingly, the transistor dimensions in the post-layout netlist file are then modified by a commercial software tool with a pattern search function. Comparing with the model based approach, the lookup table approach takes much less time for modifying the post-layout netlist. The lookup table approach is flexible, since the tables can be easily updated to reflect the most recent process changes from the foundry. In summary, a lookup table based approach for improving the post-layout verification accuracy is described. This approach can improve the verification accuracy from both litho and non-litho process variations. This approach has been applied to Xilinx's 65 nm and 45 nm product developments.

SPIE Journal Paper | 1 July 2007

Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house's approach

Jonathan Ho, Yan Wang, Joanne Wu, Ya-Ching Hou, Ke-Chih Wu

JM3, Vol. 6, Issue 03, 031008, (July 2007) https://doi.org/10.1117/12.10.1117/1.2781584

KEYWORDS: Optical proximity correction, Design for manufacturability, Lithography, Design for manufacturing, Metals, Scanning electron microscopy, Semiconducting wafers, Holmium, Calibration, Integrated circuit design

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Proceedings Article | 21 March 2007 Paper

A simple and practical approach for building lithography simulation models using a limited set of CD data and SEM pictures

Yan Wang, Jonathan Ho, Benjamin Lin, C.-L. Lin, Y.-C. Sheng, Yoyi Gong, Steven Hsu, Kechih Wu

Proceedings Volume 6521, 65211S (2007) https://doi.org/10.1117/12.712392

KEYWORDS: Data modeling, Calibration, Scanning electron microscopy, Critical dimension metrology, Lithography, Optical proximity correction, Cadmium, Semiconducting wafers, Process modeling, Optical calibration

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Proceedings Article | 21 March 2006 Paper

Inverse lithography technology at chip scale

Benjamin Lin, Ming Feng Shieh, Jie-wei Sun, Jonathan Ho, Yan Wang, Xin Wu, Wolfgang Leitermann, Orson Lin, Jason Lin, Yong Liu, Linyong Pang

Proceedings Volume 6154, 615414 (2006) https://doi.org/10.1117/12.656827

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Manufacturing, Scanning electron microscopy, Calibration, Image quality, Semiconducting wafers, Image processing, Semiconductors

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Proceedings Article | 14 March 2006 Paper

DFM: a practical layout optimization procedure for the improved process window for an existing 90-nm product

Jonathan Ho, Yan Wang, Ya-Ching Hou, Benjamin Szu-Min Lin, Chun Chi Yu, Kechih Wu, Cliff Ma

Proceedings Volume 6156, 61560C (2006) https://doi.org/10.1117/12.656085

KEYWORDS: Design for manufacturing, Optics manufacturing, Optical simulations, Optical proximity correction, Critical dimension metrology, Field programmable gate arrays, Metals, Scanning electron microscopy, Diffraction, Microelectronics

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Proceedings Article | 9 November 2005 Paper

FPGA chip performance improvement with gate shrink through alternating PSM 90nm process

Chun-Chi Yu, Ming-Feng Shieh, Erick Liu, Benjamin Lin, Jonathan Ho, Xin Wu, Petrisor Panaite, Manoj Chacko, Yunqiang Zhang, Wen-Kang Lei

Proceedings Volume 5992, 59925A (2005) https://doi.org/10.1117/12.637426

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Critical dimension metrology, Design for manufacturing, Halftones, Manufacturing, Semiconducting wafers, Image processing, Field programmable gate arrays

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Proceedings Article | 5 November 2005 Paper

Real-world impacts of inverse lithography technology

Jonathan Ho, Yan Wang, Xin Wu, Wolfgang Leitermann, Benjamin Lin, Ming Feng Shieh, Jie-wei Sun, Orson Lin, Jason Lin, Yong Liu, Linyong Pang

Proceedings Volume 5992, 59921Z (2005) https://doi.org/10.1117/12.632211

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Manufacturing, Scanning electron microscopy, Calibration, Image quality, Semiconducting wafers, Semiconductors, Image segmentation

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Proceedings Article | 5 May 2005 Paper

DFM in practice: results of a three way partnership between a leading fabless design house, foundry, and EDA company to implement alternating-phase shift mask (Alt-PSM) on a 90-nm FPGA chip

Chun-Chi Yu, Ming-Feng Shieh, Erick Liu, Benjamin Lin, Henry Lin, Manoj Chacko, Xiaoyang Li, Wen-Kang Lei, Jonathan Ho, Xin Wu

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.598838

KEYWORDS: Photomasks, Design for manufacturing, Optical proximity correction, Critical dimension metrology, Image processing, Manufacturing, Electronic design automation, Etching, Halftones, Lithography

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Showing 5 of 10 publications

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