Over the last decade the design and reactive ion etch based fabrication of a range of innovative Si and SiO2 MEMS based optical transmission devices has significantly increased. These devices rely on the principle that the data contained within the transmitted light retains its integrity, hence it is important that the reflected light does not suffer interference and losses from the surface used to direct it. To achieve this, reflecting surfaces need to be as smooth as possible, without compromising processing etch rate, sidewall profile and cross-wafer uniformity. This paper describes the results of recent hardware and process development trials using time multiplexed silicon ICP etch processing (STS ASE) at reduced switching times to provide vertical sidewalls at less than 10nm RMS roughness. For dielectric etch optical applications requiring high aspect ratio (>10:1) or through wafer depth capability (400mm at 1.2μm/min), we also report the results of process development trials using STS Advanced Oxide Etch (AOE) technology.
Mark McNie, Christopher Pickering, Alexandra Rickard, Iain Young, Janet Hopkins, Huma Ashraf, Serrita McAuley, Glenn Nicholls, Richard Barnett, Fred Roozeboom, Anton Kemmeren, Eric Van Den Heuvel, Jan Verhoeven, Colin Gormley, Paulo Schina, Corrado Di Luciano, Jyrki Kiihamaki
Over the last 5 years, deep dry etching of silicon has developed into a mainstream microsystems process technology. To transition from R&D into production, some of the main issues to address are the CoO (cost of ownership), reliability and reproducibility of capital equipment. Commensurate with this, it is essential to achieve high etch rates with good profile control. MICROSPECT (Microsystems Production Evaluated Cluster Tool), a project within the EC SEA programme, has sought to address these issues. The project has evaluated and significantly enhanced the performance of STS ASE modules for deep dry etching on an ASPECTHR production cluster platform.
The development phase of the project has provided an ideal opportunity for the equipment supplier to test and respond to feedback on the tool and the latest hardware and software developments with multiple end users, including a new high density inductively coupled plasma (ICP) source. This has resulted in higher etch rates for greater throughput and improved profile control across a variety of applications, including silicon-on-insulator (SOI)-based MEMS and microfluidics. During the evaluation phase, the system was operated under close-to-production conditions to establish system reliability and metrics.
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