Inverse lithography technology (ILT) was studied during process development for four layers from memory semiconductor designs. This paper describes techniques used in each of the layers. So as to demonstrate this technology in a wide range of semiconductor patterns, we show results from all four layers. Polysilicon was chosen to demonstrate the selection of exposure/defocus (ED) points for constraining the inversion. Marking process window boundaries during a mask creation run was demonstrated on a contact hole layer. With a deep trench layer, mask constraints were varied and write times studied. Lastly, wafer SEM images were collected for an active layer to explore image fidelity though focus and CD stability along a line.
Progressive mask defect problem is an industry wide mask reliability issue. During the start of this problem when the defects on masks are just forming and are still non-critical, it is possible to continue to run such a problem mask in production with relatively low risk of yield impact. But when the defects approach more critical state, a decision needs to be made whether to pull the mask out of production to send for clean (repair). As this problem increases on the high-end masks running DUV lithography where masks are expensive, it is in the interest of the fab to sustain these problem masks in production as long as possible and take these out of production only when absolutely necessary; i.e., when the defects have reached such a critical condition on these masks that it will impact the process window. During the course of this technical work, investigation has been done towards understanding the impact of such small progressive defects on process window. It was seen that a small growing defect may not print at the best focus exposure condition, but it can still influence the process window and can shrink it significantly. With the help of a high-resolution direct reticle inspection, early detection of these defects is possible, but fabs are still searching for a way to disposition (make a go / no-go decision) on these defective masks. But it is not an easy task as the impact of these defects will depend on not only their size, but also on their transmission and MEEF. A lithographic detector has been evaluated to see if this can predict the criticality of such progressive mask defects.
The model-based OPC is considered in 0.13um and beyond generation. However, the accuracy of model-based OPC is based on the measurement of test patterns on bare silicon wafers using the optimized exposure condition. The through pitch patterns and systematic patterns should be contained in the test patterns design. Experiments showed that the accuracy of model would be constrained if the underlying pattern effects would not be considered. The CD performance at the defocus and process window would also suffer since not considering the underlying pattern effects. This CD performance at defocus level and process window will be worse at damascene process. In this paper, we propose a hybrid OPC to cover these issues. In this work, we can use a simple method to investigate the underlying impact on the target layer on which we want to implement OPC to improve the pattern fidelity. We can observe the impact of underlying layer by studying the CD of critical patterns at de-focus level. This experiment provides us the CD data for considering the underlying impact without relying on theoretical foundation. With the hybrid OPC, we can find the exposure latitude has been improved
Data preparation of photomask layout has become a major issue of mask making. As model-based OPC becomes a compulsory technology for advanced manufacturing processes, photolithography engineers encounter the issue in data preparation of photomask layout - the file size after-OPC treatment is much larger than original file size. Consequence of large file size leads to difficult manipulation of database such as longer OPC run time and larger disk space, which challenges computer system and software tools, etc. Part of file-size expansion arises from the nature of current methodology, which is caused by fragmentation of polygon edges. However, still part of expansion is unnecessary, because some unintentional layout is sent into an OPC engine. If any given OPC engine is fed with unintentional layout features produced after OPC is applied on layouts, a systematic 'smoothing' algorithm is developed to apply on a real chip. Any algorithms that scan through polygons for each type of defects would be unavoidable to scan the whole layout many times. The algorithm introduced here does not try to fix different kinds of polygon 'defects' one by one. The key is different kinds of defects are reduced to a few categories. The performance can be expected because polygons are scanned through fewer times. After the treatment, the numbers of polygon vertices becomes less. The new database is also more OPC friendly.
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