In the realm of Design for Manufacturability (DFM) optimization, Pattern-Based Layout Optimization (PBLO) has been a go-to approach for detecting and repairing DFM violations. However, to enhance the effectiveness of DFM rules in addressing hotspots, it becomes imperative to encompass a broader array of design situations (layout contexts). This expansion leads to an increased number of potential fixing guidance “hints”. Nonetheless, employing a static fixing hint order, unaware to the specific in-design topologies, can potentially diminish the output metrics i.e., fixing rate and runtime performance. In pursuit of optimizing these output metrics, we present an ML-powered PBLO workflow. In this innovative approach, a Machine Learning (ML) model is trained using an extensive dataset of preranked fixing guidance hints that are associated with a DFM rule. The topology aware supervised ML model is trained to dynamically guide and select the most suitable in-design fixing guidance order per situation, ultimately leading to an improved fixing rate, runtime and quality of results. In this study, we illustrate a workflow and mechanism for seamlessly integrating machine learning capabilities into the in-design fixing router. This involves developing multiclass machine learning algorithms and models to facilitate the generation of an optimal fixing guidance sequence.
A pattern replacement in-design auto-fixing methodology, called MAS-POP, is developed to increase the scores calculated by the Manufacturability Analysis and Scoring (MAS) tool, improving the compliance with DFM rules. A library of patterns is developed using pattern classification automation, converting multiple types of Back-End-Of-Line (BEOL) DFM rules to patterns: via-metal line end enclosure, metal 2 tip-to-tip spacing, and metal area. Corresponding fixing hints are prescribed for each pattern. Once the library of patterns and the associated fixing hints have been developed, they are integrated with the router to utilize its pattern replacement feature. This insertion identifies matching patterns and fixes the violations by applying the prescribed fixing hints, improving the usage of the DFM rules and enhancing the MAS scores. The MAS-POP methodology is demonstrated on routed designs. Results show that for a 200 x 200 um2 block, three via-metal line end enclosure patterns reduce the number of DFM violations from 12.5k to 360 on one 2x metal layer, with a small runtime impact.
KEYWORDS: Data modeling, Machine learning, Neural networks, Design and modelling, Design for manufacturing, Principal component analysis, Correlation coefficients, Singular value decomposition, Mathematical optimization, Lithography
Design for Manufacturability (DFM) physical verification checks using supervised Machine Learning (ML) are developed and optimized to identify via-metal enclosure weak points to prevent via opens caused by line-end shortening post-retargeting. Various methods for generating feature vectors and neural network architectures are evaluated for optimizing training time and ML model quality. Techniques include applying PCA to image-based density vectors generated from layout clips to identify the principle components or using localized layout features directly for model training. Results show that for a sample size of 300k vias, the image-based density vectors versus localized layout feature vectors achieve similar correlation coefficients of 0.95 and normalized RMSE of 0.11, with a training time of 10+ hours versus 1+ minute, respectively.
Design for Manufacturability (DFM) in-design fixing methodologies are developed to improve Manufacturability Aware Scoring (MAS). Two methodologies have been evaluated. For the first methodology, DFM recommended rules are inserted in the reference flow for rip-up-and-reroute, thus fixing DFM rule violations, improving the MAS score. For the second methodology, pattern classification is used to classify the recommended rules into patterns based on the profiling of multiple layout designs. A library of fixable patterns with corresponding fixes is built. The pattern library is then inserted in the rip-up-and-reroute flow to fix the DFM rule violations, improving the MAS score. The methodologies are demonstrated on 28nm technology. Results show an average fix rate of 89.1 % for a design with a core utilization of 0.6 and 78.4% with a core utilization of 0.6 for three DFM MAS enclosure rules, VIA2, VIA3 and VIA4 layers.
This work is evaluating Machine Learning (ML) architecture options for weak point detection methods embedded in Design for Manufacturing (DFM) signoff tools. As Deep Learning based models have been released into the customer design enablement space, we are investigating the tradeoffs between model simplicity, run time and prediction accuracy. With simpler model architectures, additional options for data augmentation become available that can potentially result in better model accuracy. For example, noise introduction in the training data set can help prevent overfitting and thus results in better model accuracy.
This paper demonstrates a new approach for hotspot detection in large design spaces. We present a new pattern matching technique, which is a multi-window pattern search that is deployed in a dynamic and precise way to search for similar patterns. Based on the matched locations the flow extracts and combines silicon awareness features and design level features to build comprehensive feature matrix that can be used in subsequent analytical analysis. The paper also shows the advantage of using this flow with respect to precise capture of hotspot and ~10X improvement on turnaround time for feature extraction compared with traditional methods. The output of this flow also facilitates and improves the data preparation process for machine learning model building.
Retargeting-aware Design for Manufacturability (DFM) via-metal enclosure checks are developed using supervised machine learning to identify critical weak points to aid layout fixing. The machine learning model is developed using a neutral network architecture. Seventeen localized layout features were extracted, including: side and line end via-metal enclosure, via spacing to the neighboring features, and metal coloring. The extracted features were used to form feature vectors to train and generate a machine learning-based model for predicting post-retargeting, via-metal enclosures. This method was demonstrated on 22nm layouts. Using a neural network with 2-hidden layers, the predicted via-metal enclosure versus the actual data correlate with an R2 of 0.91 and an RMSE 0.0067.
Two-dimensional pattern matching libraries are used to define known hotspots in the design space. These libraries can then be integrated into a physical design router to search and fix such hotspots prior to the design being completed and signed off. The task of searching for similar patterns to the known hotspot involves a significant manual effort in pattern match library development. This paper demonstrates an automated and comprehensive approach to profile the available design space for similar topological patterns based on the known hotspot and automatically generate a comprehensive master pattern library to fix and address the hotspot issue. This paper presents a semi-supervised learning algorithm for developing pattern similarity metric for pattern similarity ranking and clustering.
With more advanced semiconductor technologies, identifying process weak points becomes more complex as multiple layers need to be taken into consideration. In recent years, traditional rule based weak point identification has been augmented by pattern matching to pinpoint and fix possible design weak points. Traditional methods of pattern definition are done by profiling the designs for weak points to capture the patterns of interest for applying opportunistic fixes. Patterns are usually handcrafted by taking process information into account, and applying fixes on the design features. Some fail modes have emerged recently that are a result of very complex multi layer interactions. These types of weak points are very difficult to define comprehensively with traditional pattern matching.
Recently, deep learning has undergone a rapid development and tools are now available that can learn based on large amounts of process data. We have harnessed this to address the problem of identifying complex weak points with low escape rates. In this paper, we provide a review on a deep learning based weak point detection flow taking retargeting/opc/orc simulations into account as training data. Using the deep learning approach, the process data is abstracted as an encrypted machine learning model, and released to designers as part of the GLOBALFOUNDRIES (GF) DRC+ tool. This tool is shipped with the PDK, and can be used to fix the design, mitigating process weak points.
This paper begins with a brief introduction to the deep learning TensorFlow model using Convolutional Neural Network (CNN) widely used for image detection. Then we focus on feature density vector (DSV) generation to extract the layout parameters and labels used for training the model. Experimental analysis is also provided to compare recall and precision metrics of POR and ML methods in detecting the weak point on a via layer at process window conditions. Our case study shows that the ML flow improves the pattern capture rate by 34% over standard hotspot detection methods. As a conclusion, we will also brief on our future work leveraging the ML flow for other weak point detections.
With multi patterning being the method of choice for pushing technology further down the shrink roadmap, new design weak points are emerging that have multi-layer components and are difficult to find and to define. On the other hand, advanced OPC methodologies like retargeting and recentering help alleviate many of the occurrences, leaving only a few locations that are critical and need to be dealt with in design. State of the art in-design weak point auto fixing is usually done by identifying a weak point by a pattern match, and providing the router either a “safe” alternative configuration or tell it to reroute locally, also called rip-and-reroute. The dilemma for developing pattern matching decks that are used in place and route tools is that one cannot be too specific in the pattern definition as there will be escapes that can possibly cause problems in the fab. Having a more general pattern definition will prevent escapes, but will flag many locations that don’t really require fixing. As a consequence, this more general pattern definition may bog down the place and route tool and can actually result in area bloat if too many rip-and-reroute areas are identified. We have come up with a patented flow that allows very specific weak point detection with a low escape rate. The flow starts with a generic pattern definition of the fail mode, but reduces the number of occurrences by identifying safe configurations. Usually, the pattern extent of the safe configuration is larger than the initial generic pattern, and may contain more layers. Any known safe configuration is added to a “good pattern” database which is then subtracted from the initial pattern match. Thus, the number of design locations that need to be auto fixed is kept at a minimum. As the technology matures, more safe patterns are found and added to the database, thus reducing the amount of auto fixing required.
Via failure has always been a significant yield detractor caused by random and systematic defects. Introducing redundant vias or via bars into the design can alleviate the problem significantly [1] and has, therefore, become a standard DFM procedure [2]. Applying rule-based via bar insertion to convert millions of via squares to via bar rectangles, in all possible places where enough room could be predicted, is an efficient methodology to maximize the redundancy rate. However, inserting via bars can result in lithography hotspots. A Pattern Manufacturability (PATMAN) model is proposed, to maximize the Redundant Via Insertion (RVI) rate in a reasonable runtime, while insuring lithography friendly insertion based on the accumulated DFM learnings during the yield ramp.
Lithography process variation as well as etch and topography have always been a stubborn challenge for advanced technology nodes, i.e. 14nm and beyond. This variability usually results in defects aggregating around the edge of the wafer and leading to yield loss. A very tight process control is the logical resolution for such issues, nevertheless it might not be possible, or it may slow down the whole design to silicon cycle time. Another degree of difficulty is detecting these defects in ORC and concluding an OPC fix. In this paper, we show that aerial image ORC checks could provide a very useful insight to these defects ahead of time, and that they correlate well with silicon defects highlighted by CFM scan. This early detection upstream enables us to conclude a generic OPC fix for such issues and also improves the total OPC process-window enhancement and eliminates these defects on silicon.
At advanced technology nodes (sub-22 nm), design rules become very complicated as interactions between multiple layers become more complex, while the number of design elements within the optical radius increases. As a result, one may possibly encounter novel yield limiters in the 2D/3D design space with every new product taping out to the fab. Key to fast yield ramp is identifying novel constructs that may become yield detractors, and to address the challenge in the DFM space before actual Silicon is run. A comprehensive methodology to find such geometric constructs is proposed.
Optical Proximity Correction (OPC) is a compute-intensive process used to generate photolithography mask shapes at advanced VLSI nodes. Previously, we reported a modified two-step OPC flow which consists of a first pattern replacement step followed by a model based OPC correction step [1]. We build on this previous work and show how this hybrid flow not only improves full chip OPC runtime, but also significantly improves mask correction consistency and overall mask quality. This is demonstrated using a design from the 20nm node, which requires the use of model based SRAF followed by model based OPC to obtain the full mask solution.
KEYWORDS: Statistical analysis, Very large scale integration, Profiling, Data modeling, Databases, Metals, Data mining, Data processing, Data storage, Visualization
Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.
Techniques to control Across Chip CD Variation are very important in IC design, since it directly impacts the electrical timing and
functionality of the designs. VLSI designs today include a rich variety of electrical devices (different gate oxide thicknesses, different
threshold voltages, etc.) to provide the much needed flexibility to the chip designer. These devices occur at different proximities and
different densities on a full chip design. In this paper, we describe a method for improving and ensuring design-to-mask (D2M) quality
via a quantitative relationship between design specification and full chip tapeout results. This is done by applying a layout profiling
technique with the aim of capturing comprehensive representation of the design space, this method ensures the quality of design-to-mask
flow prior to release OPC data to mask house.
A methodology is described wherein a calibrated model-based ‘Virtual’ Variable Shaped Beam (VSB) mask writer
process simulator is used to accurately verify complex Optical Proximity Correction (OPC) and Inverse Lithography
Technology (ILT) mask designs prior to Mask Data Preparation (MDP) and mask fabrication. This type of
verification addresses physical effects which occur in mask writing that may impact lithographic printing fidelity
and variability. The work described here is motivated by requirements for extreme accuracy and control of
variations for today’s most demanding IC products. These extreme demands necessitate careful and detailed
analysis of all potential sources of uncompensated error or variation and extreme control of these at each stage of
the integrated OPC/ MDP/ Mask/ silicon lithography flow. The important potential sources of variation we focus on
here originate on the basis of VSB mask writer physics and other errors inherent in the mask writing process. The
deposited electron beam dose distribution may be examined in a manner similar to optical lithography aerial image
analysis and image edge log-slope analysis. This approach enables one to catch, grade, and mitigate problems early
and thus reduce the likelihood for costly long-loop iterations between OPC, MDP, and wafer fabrication flows. It
moreover describes how to detect regions of a layout or mask where hotspots may occur or where the robustness to
intrinsic variations may be improved by modification to the OPC, choice of mask technology, or by judicious design
of VSB shots and dose assignment.
Full chip model based Optical Proximity Correction (OPC) at
advanced nodes involves iteratively modifying the drawn polygon shapes
while simulating them through complex optical and resist models. Due to
the computational complexity of the models and the large size of VLSI
designs, these mask simulations run for very long times. In this study we
propose a pattern replacement step to generate a partial mask solution
before applying model based OPC correction. Since the pattern replacement
step is very fast and model based OPC has to be applied only to a
portion of the design, total mask generation runtime is significantly reduced.
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