Mr. Harm Dillen Profile

Harm Dillen

System Engineer at ASML Netherlands BV

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Publications (12)

Proceedings Article | 10 April 2024 Presentation + Paper

Feature grouping to enable edge placement error-aware process control in multi-feature logic use case

Guillaume Schelcher, Marsil Athayde, Stijn Schoofs, Jeff Hsia, Zuan Khalik, Fahong Li, Konstantin Nechaev, Reza Sahraeian, Amir-Hossein Tamaddon, Victor Blanco, Stefan van der Sanden, Yichen Zhang, Roy Anunciado, Harm Dillen, Philippe Leray

Proceedings Volume 12955, 129550O (2024) https://doi.org/10.1117/12.3010421

KEYWORDS: Semiconducting wafers, Overlay metrology, Cross validation, Process control, Logic, Metrology, Simulations, Scanning electron microscopy, Lithography

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Proceedings Article | 30 April 2023 Presentation

The edge placement error characterization and optimization for advanced logic and DRAM nodes

Harm Dillen, Wim Tel, Jaap Karssenberg, Jan Mulkens, Roy Anunciado, Yichen Zhang, Konstantin Nechaev, Zuan Khalik

Proceedings Volume 12496, 124960O (2023) https://doi.org/10.1117/12.2658832

KEYWORDS: Overlay metrology, Logic, Optical proximity correction, Metrology, Stochastic processes, Semiconductors, Semiconductor manufacturing, Scanners, Manufacturing, Line edge roughness

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Proceedings Article | 20 March 2020 Presentation + Paper

Understanding advanced DRAM edge placement error budget and opportunities for control

Jaeseung Jeong, Jinho Lee, Jinsun Kim, Sunyoung Yea, Chan Hwang, Seung Yoon Lee, Jeongjin Lee, Joonsoo Park, Peter Nikolsky, Daniel Park, Antonio Corradi, Hyun-Woo Yu, Sun-Wook Jung, Denis Ovchinnikov, Vadim Timoshkov, Isabel de la Fuente Valentin, Yuxiang Yin, Kaustubh Padhye, Wim Tel, Harm Dillen, Koen Thuijs, Daan Slotboom, Miao Wang, Rhys Su, Marc Kea, Jin-Woo Lee, Yun-A Sung, Sang-Uk Kim, Young-Hoon Song, James Lee, Oh-Sung Kwon

Proceedings Volume 11325, 1132506 (2020) https://doi.org/10.1117/12.2551997

KEYWORDS: Metrology, Critical dimension metrology, Semiconducting wafers, Stochastic processes, Optical lithography, Etching, Lithography, Edge roughness

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Proceedings Article | 26 March 2019 Paper

Analyze line roughness sources using power spectral density (PSD)

Lingling Pu, Teng Wang, Thomas Huisman, Ruben Maas, Maikel Goosen, Harm Dillen, Philippe Leray, Wei Fang

Proceedings Volume 10959, 109592W (2019) https://doi.org/10.1117/12.2516570

KEYWORDS: Scanning electron microscopy, Line edge roughness, Semiconducting wafers, Monte Carlo methods, Image segmentation, Semiconductors, Extreme ultraviolet, Optical simulations, Solids, Metrology

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Proceedings Article | 26 March 2019 Presentation

Massive metrology and failure identification for DRAM applications (Conference Presentation)

Harm Dillen, Dorothe Oorschot, Marleen Kooiman, Willem van Mierlo, Ziyang Wang, Kang-San Lee, Jin-Woo Lee, Ruochong Fei, Shu-Yu Lai, Marc Kea, Inhwan Lee, Hwan Kim, Junghyun Kang, Jaehee Hwang, Chang-Moon Lim

Proceedings Volume 10959, 109591K (2019) https://doi.org/10.1117/12.2515487

KEYWORDS: Failure analysis, Critical dimension metrology, Metrology, Extreme ultraviolet lithography, Printing, Semiconducting wafers

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Introduction and problem statement Given that EUV lithography allows printing smaller Critical Dimension (CD) features, it can result in non-normal distributed CD populations on ADI wafers [Civay SPIE AL 2014], leading to errors in predicted failure rates [Bristol SPIE AL 2017]. As a result, there is a need to quantify the actual behavior of the CD population extremes by means of massive metrology [Dillen EUVL 2018]. Not only allows this to study the CD distribution, we can in parallel also evaluate pattern quality and the failure mechanisms leading to defects. This massive metrology method provides an accurate failure rate based on CD, and enables new possibilities to define a failure rate based on different metrics in a single measurement. Method We analyze the CD uniformity of pillars in polar coordinates using a global waveform based thresholding strategy. In conjunction with this CD information, we also evaluated the print quality of each individual measured feature. Fig 1. In line detected anomalies and failure definitions As we gather this information during the measurement of CD, we can limit the additional measurement overhead to neglectable levels. Application and outlook We will show how we can leverage this to determine a defect based process window and relations of failure mechanisms through process conditions (see figure 2). When we take failures in a CH dataset into account, we illustrate the effect on the shape of a large dataset distribution in figure 3. Fig 2. Defect identification for a through exposure dose experiment of pillars. For each condition >13k pillars where measured. The plot clearly shows an asymmetric behavior due to different failure mechanisms at low and high energy. The 2 vertical lines at relative energies 0.93 and 1.05 times nominal indicate the low defect process window. Fig 3. A distribution of measured regular grid dense CH. The red line is the unfiltered CD data, the blue line is the shape of the distribution after filtering individual CH measurements that have a much lower contrast than expected.

Proceedings Article | 3 October 2018 Presentation + Paper

Massive CD metrology for EUV failure characterization and EPE metrology

Harm Dillen, Yi-Hsin Chang, Fei Wang, Marc Kea, Gijsbert Rispens, Marleen Kooiman, Fuming Wang, Stefan Hunsche, Daniel Tien, Peng Tang, Pengcheng Zhang

Proceedings Volume 10809, 108090C (2018) https://doi.org/10.1117/12.2502495

KEYWORDS: Critical dimension metrology, Metrology, Cadmium, Extreme ultraviolet, Failure analysis, Finite element methods, Scanning electron microscopy, Extreme ultraviolet lithography

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Proceedings Article | 13 March 2018 Presentation + Paper

Holistic approach for overlay and edge placement error to meet the 5nm technology node requirements

Jan Mulkens, Bram Slachter, Michael Kubis, Wim Tel, Paul Hinnen, Mark Maslow, Harm Dillen, Eric Ma, Kevin Chou, Xuedong Liu, Weiming Ren, Xuerang Hu, Fei Wang, Kevin Liu

Proceedings Volume 10585, 105851L (2018) https://doi.org/10.1117/12.2297283

KEYWORDS: Metrology, Overlay metrology, Scanners, Semiconducting wafers, Extreme ultraviolet lithography, Logic, Optical proximity correction, Lithography, Critical dimension metrology, Electron beams

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Proceedings Article | 28 April 2017 Presentation

CD-SEM metrology and OPC modeling for 2D patterning in advanced technology nodes (Conference Presentation)

Thomas Wallow, Chen Zhang, Anita Fumar-Pici, Jun Chen, Bart Laenens, Christopher Spence, David Rio, Paul van Adrichem, Harm Dillen, Jing Wang, Peng-Cheng Yang, Werner Gillijns, Patrick Jaenen, Frieda van Roey, Jeroen van de Kerkhove, Sergey Babin

Proceedings Volume 10145, 101451Q (2017) https://doi.org/10.1117/12.2260443

KEYWORDS: Metrology, Optical proximity correction, Data modeling, Optical lithography, Signal to noise ratio, OLE for process control, Instrument modeling, Image analysis, Calibration, Metals

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In the course of assessing OPC compact modeling capabilities and future requirements, we chose to investigate the interface between CD-SEM metrology methods and OPC modeling in some detail. Two linked observations motivated our study: 1) OPC modeling is, in principle, agnostic of metrology methods and best practice implementation. 2) Metrology teams across the industry use a wide variety of equipment, hardware settings, and image/data analysis methods to generate the large volumes of CD-SEM measurement data that are required for OPC in advanced technology nodes. Initial analyses led to the conclusion that many independent best practice metrology choices based on systematic study as well as accumulated institutional knowledge and experience can be reasonably made. Furthermore, these choices can result in substantial variations in measurement of otherwise identical model calibration and verification patterns. We will describe several experimental 2D test cases (i.e., metal, via/cut layers) that examine how systematic changes in metrology practice impact both the metrology data itself and the resulting full chip compact model behavior. Assessment of specific methodology choices will include: • CD-SEM hardware configurations and settings: these may range from SEM beam conditions (voltage, current, etc.,) to magnification, to frame integration optimizations that balance signal-to-noise vs. resist damage. • Image and measurement optimization: these may include choice of smoothing filters for noise suppression, threshold settings, etc. • Pattern measurement methodologies: these may include sampling strategies, CD- and contour- based approaches, and various strategies to optimize the measurement of complex 2D shapes. In addition, we will present conceptual frameworks and experimental methods that allow practitioners of OPC metrology to assess impacts of metrology best practice choices on model behavior. Finally, we will also assess requirements posed by node scaling on OPC model accuracy, and evaluate potential consequences for CD-SEM metrology capabilities and practices.

Proceedings Article | 28 March 2017 Presentation + Paper

CD-SEM distortion quantification for EPE metrology and contour analysis

Harm Dillen, Ton Kiers, Sandip Halder, Thomas Wallow, Frieda van Roey

Proceedings Volume 10145, 1014515 (2017) https://doi.org/10.1117/12.2260664

KEYWORDS: Distortion, Scanning electron microscopy, Metrology, Data corrections, Image quality, Tolerancing, Optical proximity correction, Optical lithography, Visualization, Critical dimension metrology, Data modeling, Semiconducting wafers, Distance measurement, Error analysis, Calibration, Mathematical modeling, Performance modeling

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Proceedings Article | 26 September 2016 Paper

YieldStar based reticle 3D measurements and its application

Vidya Vaenkatesan, Jo Finders, Peter ten Berge, Reinder Plug, Anko Sijben, Twan Schellekens, Harm Dillen, Wojciech Pocobiej, Vasco Jorge, Jurgen van Dijck

Proceedings Volume 9985, 99850M (2016) https://doi.org/10.1117/12.2242857

KEYWORDS: Reticles, Critical dimension metrology, 3D metrology, Photomasks, Metrology, Semiconducting wafers, Extreme ultraviolet, Scanning electron microscopy, EUV optics, Wafer-level optics

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Proceedings Article | 25 March 2016 Paper

Material analysis techniques used to drive down in-situ mask contamination sources

Harm Dillen, Gerard Rebel, Jennifer Massier, Dominika Grodzinka, Richard Bruls

Proceedings Volume 9778, 97781N (2016) https://doi.org/10.1117/12.2220400

KEYWORDS: Particles, Chemical elements, Spectral resolution, Photomasks, Materials analysis, Scanning electron microscopy, Extreme ultraviolet lithography, Scanners, Associative arrays, Contamination control, Particle contamination, Defect inspection, Sensors, Electron beams, X-rays, Silicon carbide, Silicon, Chromium

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Proceedings Article | 4 September 2015 Paper

YieldStar based reticle 3D measurements and its application

Vidya Vaenkatesan, Twan Schellekens, Natalia Davydova, Harm Dillen, Joep van Dijk

Proceedings Volume 9661, 96610N (2015) https://doi.org/10.1117/12.2196665

KEYWORDS: Reticles, Semiconducting wafers, Critical dimension metrology, Extreme ultraviolet, 3D modeling, Ions, Resolution enhancement technologies, 3D metrology, Metrology, Scanners

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Showing 5 of 12 publications

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