High-defect density in thermodynamics driven directed self-assembly (DSA) flows has been a major cause of concern for a while and several questions have been raised about the relevance of DSA in high-volume manufacturing. The major questions raised in this regard are: (1) What is the intrinsic level of DSA-induced defects? (2) Can we isolate the DSA-induced defects from the other processes-induced defects? (3) How much do the DSA materials contribute to the final defectivity and can this be controlled? (4) How can we understand the root causes of the DSA-induced defects and their kinetics of annihilation? (5) Can we have block copolymer anneal durations that are compatible with standard CMOS fabrication techniques (in the range of minutes) with low-defect levels? We address these important questions and identify the issues and the level of control needed to achieve a stable DSA defect performance.
The double patterning (DPT) process is foreseen by the industry to be the main solution for the 32 nm technology node
and even beyond. Meanwhile process compatibility has to be maintained and the performance of overlay metrology has
to improve. To achieve this for Image Based Overlay (IBO), usually the optics of overlay tools are improved. It was also
demonstrated that these requirements are achievable with a Diffraction Based Overlay (DBO) technique named SCOLTM
[1]. In addition, we believe that overlay measurements with respect to a reference grid are required to achieve the
required overlay control [2]. This induces at least a three-fold increase in the number of measurements (2 for double
patterned layers to the reference grid and 1 between the double patterned layers). The requirements of process
compatibility, enhanced performance and large number of measurements make the choice of overlay metrology for DPT
very challenging.
In this work we use different flavors of the standard overlay metrology technique (IBO) as well as the new technique
(SCOL) to address these three requirements. The compatibility of the corresponding overlay targets with double
patterning processes (Litho-Etch-Litho-Etch (LELE); Litho-Freeze-Litho-Etch (LFLE), Spacer defined) is tested. The
process impact on different target types is discussed (CD bias LELE, Contrast for LFLE). We compare the standard
imaging overlay metrology with non-standard imaging techniques dedicated to double patterning processes (multilayer
imaging targets allowing one overlay target instead of three, very small imaging targets). In addition to standard designs
already discussed [1], we investigate SCOL target designs specific to double patterning processes. The feedback to the
scanner is determined using the different techniques. The final overlay results obtained are compared accordingly. We
conclude with the pros and cons of each technique and suggest the optimal metrology strategy for overlay control in
double patterning processes.
The merits of hyper NA imaging using 193nm exposure wavelength with water immersion for 45nm is clear. Scanner
focus and dose control is always improving to allow small DOF manufacturing in immersion lithography. However,
other process parameters can affect focus and dose control and a real-time monitor capability to detect local focus and
exposure conditions on production wafers is required. In this paper we evaluated a focus-exposure monitor technique
based on Spectroscopic Critical Dimension (SCD) metrology following the promising results obtained by Kelvin Hung
[1] et al. The key attributes of this technique are the implementation on standard production wafers, the high sensitivity
to pattern profile modifications and the unique capability of spectroscopic ellipsometry to provide all the information
needed to decouple the effects on pattern formation coming from process variations of Advanced Patterning Films (APF)
[2], largely adopted for 65/45nm patterning, from coating and, finally, from the pure scanner imaging contributors like
focus and exposure. We will present the characterization of this technique for 2 critical layers: active and contacts of a
non-volatile memory device, 45nm technology.
CMOS 65nm technology node requires the introduction of advanced materials for critical patterning operations. The
study is focused on the multilayer Anti Reflective Coating (ARC) stack, used in photolithography, for the gate patterning
such as Advanced Patterning Film (APF). The interest on this new and complex ARC stack lies in the benefit to
guarantee low CD dispersion thanks to a better reflectivity control and resist budget which leads to a larger lithographic
process window. However, it implies numerous metrology challenges.
The paper deals with the challenges of monitoring the gate Critical Dimension (CD) on this stack. The validation of
the scatterometry model versus stack thicknesses and indexes variations, through experiments, is also described. The
final result is the complete characterization of the materials for thickness and scatterometry CD control, for photo feedback
and for etch feed-forward deployment in an industrial mode.
The analysis shows that scatterometry measurements on a standard 65 nm gate process ensure a better effectiveness
than the CD Scanning Electron Microscopy (SEM) ones when injected in the Advanced Process Control (APC) system
from photo to etch.
Double patterning is the best technique which allows 193nm immersion lithography to anticipate the 32 nm node, before
EUV lithography. The final device pattern is formed by two independent patterning steps where the dense pitch is
doubled. This allows printing each patterning step with higher k1 imaging factor.
In this paper we present the overlay and CD budget applied to a double patterning (DP) technique for the definition of a
32nm technology node device, using an immersion scanner tool. A balance among different factors which affects the
final CD of the device is necessary to optimize the imaging and the alignment performances of the exposure tool. A
preliminary activity is also necessary to choose the most suitable mask splitting strategy. Adopting a single mask, which
is exposed twice with the appropriate shift - the final pitch - , makes the overlay between the two exposures less critical
than splitting the complementary layouts on two different masks. Finally, the CD uniformity of the pooled distributions
from the two exposures is evaluated in order to define the requested tool performances in terms of overlay, CD control
and metrology.
A potential limitation to a wider usage of the scatterometry technique for CD evaluation comes from its requirement of
dedicated regular measurement gratings, located in wafer scribe lanes. In fact, the simplification of the original chip
layout that is often requested to design these gratings may impact on their printed dimension and shape. Etched gratings
might also suffer from micro-loading effects other than in the circuit. For all these reasons, measurements collected
therein may not represent the real behavior of the device. On the other hand, memory devices come with large sectors
that usually possess the characteristics required for a proper scatterometry evaluation. In particular, for a leading edge
flash process this approach is in principle feasible for the most critical process steps. The impact of potential drawbacks,
mainly lack of pattern regularity within the tool probe area, is investigated. More, a very large sampling plan on features
with equal nominal CD and density spread over the same exposure shot becomes feasible, thus yielding a deeper insight
of the overall lithographic process window and a quantitative method to evaluate process equipment performance along
time by comparison to acceptance data and/or last preventive maintenance. All the results gathered in the device main
array are compared to those collected in standard scatterometry targets, tailored to the characteristics of the considered
layers in terms of designed CD, pitch, stack and orientation.
KEYWORDS: Overlay metrology, Metrology, Image segmentation, Front end of line, Semiconducting wafers, Chemical mechanical planarization, Metals, Lithography, Scanning electron microscopy, Scanners
Accurate and precise overlay metrology is a critical requirement in order to achieve high product yield in microelectronic manufacturing. Meeting the tighter overlay measurement error requirements for 90nm technology and beyond is a dramatic challenge for optical metrology techniques using only conventional overlay marks like Bar in Bar (BiB) or Frame in Frames (FiF). New deficiencies, affecting traditional overlay marks, become evident as microlithography processes are developed for each new design rule node. The most serious problems are total measurement uncertainty, CMP process robustness, and device correlation. In this paper we will review the superior performances of grating-based AIM marks to provide a complete solution to control lithography overlay errors for new generation devices. Examples of successful application of AIM technology to FEOL and Cu-BEOL process steps of advanced non volatile memory devices manufacturing are illustrated. An additional advantage of the adoption of AIM marks is that the significant reduction of target noise versus conventional marks revealed systematic differences within the lithography cluster which were previously obscure offering a new tool to optimize litho cells. In this paper we demonstrated that AIM target architecture enables high performance metrology with design rule segmented targets - a prerequisite to have overlay marks fully compatible with design rule sensitive process steps.
As device dimensions shrink the number of parameters influencing CD increases (PEB dispersion, development uniformity, resist thickness, BARC thickness, +/- scan focus control, scanner focus control at edge of the wafer...). Separation between all these contributors is not easy using only CD-SEM measurement, and particularly with isolated lines. For high volume manufacturing (where "time is money") and in the case of litho cluster drift, a quick and accurate diagnostic capability is an advantage for minimizing tool unavailability. An important attribute of this diagnostic capability is that its implementation is on standard production wafers. The use of production wafers enables continuous monitoring and also allows a direct correlation between monitoring measurements and the impact on product.
The technology that enables this type of diagnostic capability makes use of a compact dual tone line-end-shortening based target. A key benefit to this technology is that it provides a separation of the dose and focus parameters, which leads to quicker route cause determination.
After building a calibration model and determining minimum dose and focus sensitivity, both short term and long term stability of the model is investigated. The impact of wafer topology on model prediction is also investigated in order to assess on-product monitoring capability. The main error contributors are then identified for both track and scanner and the impact on CD control is evaluated. These cluster error contributors are then varied, first separately, and then combined. Measurement results are compared to the input parameters in order to determine error detection ability, measurement accuracy and separation capability.
As Moore's law drives the semiconductor industry to tighter specifications, challenges are becoming real for overlay metrology. A lot of work has been done on the metrology tool capability to improve single-tool precision, tool-to-tool matching and Tool-Induced Shift (TIS) variability. But nowadays these contribute just a small portion of the Overlay Metrology Error (approximately 10% for 90nm technology). Unmodeled systematic, scanner noise and process variation are becoming the major contributors. In order to reduce these effects, new target design was developed in the industry, showing improvements in performance. Precision, Residual analysis, DI/FI (Develop Inspection / Final Inspection) bias and Overlay Mark Fidelity (OMF) are common metrics for measurement quality. When we come to measurement accuracy, we do not have any direct metric to qualify targets.
In the current work we evaluated the accuracy of different AIM (developed by Kla-Tencor) and Frame-In-Frame (FIF) targets by comparing them to reference “SEM” targets. The experiment was conducted using a special designed 65nm D/R reticle, which included various overlay targets. Measurements were done on test wafers with resist on etched poly printed on 248nm scanner.
The results showed that, for this "straight-forward" application, the best accuracy performance was achieved by the Non Segmented (NS) AIM target and was estimated in the order of 1.5 nm site-to-site. This is slightly more accurate than hole-based target and far more than NS FIF target in this particular case. When using the non-accurate NS FIF target, correctable parameters and maximum overlay prediction error analysis, showed up to 24nm overlay error at the edge of the wafer. We also showed that part of this accuracy error can be attributed to the non-uniformity of BARC deposition.
Using scatterometry based on Spectroscopic Ellipsometry, a complete study of Gate lithography level measurement on standard products has been conducted. Experiments were done on typical ST batches for 120, 90, and 65 nm nodes. KLA-Tencor SpectraCD SE system is used to collect and analyze line critical dimensions and profiles. A systematic correlation with Scanning Electron Microscope (SEM) is done, completed by a cross section analysis. The study also takes into account lithography defect anlysis using a specific targets with intentionally generated process failures. Our objective is to determine the sensitivity window of such measurment technique to process defect and marginal process conditions. We show that KLA-Tencor SpectraCD allows a full reconstruction of the line profile - as well as the film stack underneath it - with values that are in agreement with production control. Cpm values obtained on products demonstrate that SE based scatterometry fulfils all requirements to be integrated in a production envrionemnt and provides suitable metrology for advanced lithography process monitoring.
Reticle imaging and metrology are becoming increasingly difficult as reticle features decrease in size. This paper describes some early results of top down CD-SEM reticle imaging and metrology carried out in association with the DUV and 193 nm lithography programs at IMEC. Images of reticle features and some corresponding printed wafer patterns are presented and CD-SEM and optical measurement techniques are compared.
In this work, we investigate the role of low voltage reticle CD-SEM measurements on DUV lithography. We compare reticle measurements carried out on tow different CD-SEMs and optical measurements as typically carried out at mask shops. CD-SEM measurements using the 50 percent derivative algorithm on the KLA 8100ER CD-SEM and the 50 percent threshold algorithm on the Hitachi 6100 CD-SEM show good correlation with the optical measurements. As examples for the importance of LV CD-SEM reticle measurements we show the influence of proximity effects during reticle printing on CD variations on reticle level by comparing the values obtained on the reticle and on the wafer. Finally, we determine mask error factors. The MEF has to be taken into account to compare wafer and reticle CDs. We show that it does not change for wafer measurement after lithography and after poly-etch. The use of different metrology tools or electrical linewidth measurements does not influence the MEF.
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