Advancing technology nodes in CMOS Image Sensors (CIS) continues to drive a shrinking process to acquire higher resolution and low power consumption as well as more cost-effective production. With the sensor pixel size scaling down, a thicker photoresist (with aspect ratios greater than 10:1) is introduced to block high-energy implants with extremely localized implant profiles. Then double exposures/double focus (DE/DF) is applied to make sure the resist profile and process window is comparable or better. However, this process is a big challenge at high volume manufacturing (HVM) phase because of throughput loss. To recover it due to DE/DF, we invented SE MFI which uses two wavelengths (“colors”) generated by the KrF excimer laser to solve the problem. Due to the chromatic aberrations in the lens, the focal plane shift of different wavelength produces nearly the same result as DE/DF. However, the use of two-wavelengths brings some challenges. The first is the loss of image contrast and the second is the impact of chromatic aberrations across the slit which results in image shift and image asymmetry. In this work, we demonstrated that the use of ASML’s Tachyon KrF MFI source mask optimization (SMO) that can match the MFI SE process to DE/DF process of record (POR). We first used Tachyon Focus-Exposure Modeling plus (FEM+) to calibrate a DE resist model by using DE POR wafer data. Then we converted the DE model to a SE MFI model. At the end, we use the Tachyon MFI-SMO to optimize the SE MFI to match the DE/DF and MFI sidewall profiles through process window conditions at the center slit. We achieved making the MFI and DE/DF sidewall difference significantly smaller than other noises which can be measured on wafer at the center slit. We evaluated the chromatic aberration impact on through slit sidewall profiles also meet the specification. The through slit matching between MFI and DE/DF was further improved by through-slit mask optimization. This is done by inserting asymmetry sub resolution assist features (SRAFs). Tachyon Optical Proximity Correction plus (OPC+) can support full chip mask corrections for full-chip HVM. The above MFI technology including Tachyon optimization capability will be verified by wafer exposure via comparison between MFI and DE wafer results.
Advancing technology nodes in DRAM continues to drive the reduction of on-product overlay (OV) budget. This gives rise to the need for OV metrology with greater accuracy. However, the ever increasing process complexity brings additional challenges related to metrology target deformation, which could contribute to a metrology error. Typically, an accurate OV measurement involves several engineering cycles for target and recipe optimization. In particular, process optimization in either technology development (TD) phase or high volume manufacturing (HVM) phase might influence metrology performance, which requires re-optimization. Therefore, a comprehensive solution providing accuracy and process robustness hereby minimizing the cycle time is highly desirable. In this work, we report multi-wavelength µDBO enhanced with accuracy aware pixel selection as a solution for robust OV measurement against process changes as well as improved accuracy in HVM. Accuracy aware pixel selection is capable of tackling intra-target processing variations and is established on a multi-wavelength algorithm with immunity to target asymmetry impact. DRAM use cases in FEOL critical layers will be discussed in this paper. Superior robustness and accuracy will be demonstrated together with improved on-product OV performance, promising a process of record metrology solution in specific applications throughout the TD and HVM.
In advanced DRAM fabrication, wafer alignment is a key enabler to meet on-product overlay performance requirement. Due to the extreme complexity of patterning and integration process involved, it’s becoming a challenge to design alignment marks that can be patterned robustly through process window, meet process integration constraints, withstand large process variation or changes, and provide accurate alignment measurement, during early development. The unique tilted pattern in DRAM fabrication technology poses special challenges during both design and process phase. In this paper, we present a holistic computational approach to design robust alignment marks with ASML’s integrated Design for Control (D4C) and OPC solutions. With this integrated solution, we design a complex set of alignment marks for the entire full flow process from FEOL through BEOL, tailored by each stack of different lithography layers. In mark design stage, marks’ signal and robustness are optimized by D4C simulation, taking into account the design rule and process constraints, while patterning fidelity and process window of these marks is ensured by OPC, subject to the design rule constraints. We demonstrate that the process window (PW) of the resulting alignment marks, especially for the challenging layers with extreme off-axis illuminations and tight design constraints, are significantly improved, while simultaneously accurate and robust alignment measurements are obtained on full loop wafers.
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