Laurent Pain, M. Jurdit, Yves LaPlanche, J. Todeschini, Serdar Manakli, G. Bervin, Ramiro Palla, A. Beverina, R. Faure, X. Bossy, H. Leininger, S. Tourniol, M. Broekaart, F. Judong, K. Brosselin, P. Gouraud, Veronique De Jonghe, Daniel Henry, M. Woo, Peter Stolk, B. Tavel, F. Arnaud
The introduction of Electron Beam Direct Write lithography into production represents a
challenging alternative to reduce cost and cycle time increase induced by the introduction of new
generation nodes. This paper details the development work performed to insert transparently direct
write lithography process and alignment strategies into CMOS process flows. Finally, this
interchangeability between E-Beam and optical lithography steps offers a complete flexibility for
device architecture validation and allowed the development of a complete low cost 65nm platform
including low-power and general-purpose applications.
An easy way to pattern 65nm CD target, when optical lithography technology is not available, is to use an Electron Beam Direct Write tool (EBDW), which is well known for its high resolution patterning potentials, with the drawback of a very low throughput. Emerging techniques of electron projection lithography also propose the same patterning capability with enhanced throughput. One of the most crucial issues, when dealing with integration, is the overlay capability of the systems. This paper exposes the studies made on the overlay capability issue of the LEICA EBDW installed in STMicroelectronics (STM) production plant in Crolles (France) and proves our tool is ready to support the 65nm node technology development.
With the objective to ramp-up 65 nm CMOS production in early 2005, preliminary works have to start today to develop the basic technological in order to be correctly prepared. In the absence of commercial advanced 193 nm scanners compatible with these aggressive design rules, electron beam technology was employed for the realization of a first 6-T SRAM cell of a size of 0.69 μm2. This paper highlights the work performed to integrate E-beam lithography in this first 65 nm CMOS process flow.
In this study, it is investigated how chemical modifications of a given resist platform can induce improvements in e-beam lithographic performances. Molecular weight (Mw) as well as photo-acid generator (PAG) modifications will act as fine tuners for Sumitomo NEB-33 negative resist to match specific applications: preparation of advanced CMOS R&D architecture (highly resolving resists needed) and fast patterning for production environment (highly sensitive resists needed).
For the sub-90 nm node integrated circuits design rules, ITRS forecasts require minimal gate line width down to 55-35 nm. To reach such aggressive targets, most advanced optical lithography tools combined with all reticle enhancement techniques will be requested inducing important manufacturing cost and mask cycle time increase. In order to address prototyping market and reduce fabrication cost, shaped electron beam lithography may represent a technological alternative for cost reduction due to its high resolution and potential throughput capabilities. This paper is focused on the integration of this technology in standard ASIC plant, including resist process and overlay capabilities.
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