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This paper contains simulation results with the Siemens EDA Calibre tool and demonstrates theoretical proof that alternative mask materials bring significant gain when compared to the tantalum-based mask absorber. Firstly, we optimized the source and aerial image intensity threshold on a set of predefined clips (with SMO techniques). Secondly, we applied ILT techniques to correct for the full chip mask based on a horizontal layout of a metal logic layer on imec’s roadmap. We then compare the tantalum-based mask with the alternative masks using imaging criteria, such as DoF (depth of focus), NILS (Normalized Image log slope), EPE (edge placement error), pattern shifts through focus, process variation band, source telecentricity errors, and MEEF (mask error enhancement factor) on a variety of features in the metal logic clip to maximize the overall process window.
Single mask solution to pattern BLP and SNLP using 0.33NA EUV for next-generation DRAM manufacturing
Additions to the OPC model include accounting for anamorphic effects in the optics, mask electromagnetics, and mask manufacturing. The correction algorithm is updated to include awareness of anamorphic mask geometry for mask rule checking (MRC). OPC verification through process window conditions is enhanced to test different wafer scale mask error ranges in the horizontal and vertical directions.
This work will show that existing models and methods can be updated to support anamorphic optics without major changes. Also, the larger mask size in the Y direction can result in better model accuracy, easier OPC convergence, and designs which are more tolerant to mask errors.
While the EPE from variation in aberrations across the exposure field is correctable in OPC software, there are no known ways to address tool-to-tool aberration variation. Given that foundries are expected to have multiple EUV tools for high volume manufacturing, the degree of tool-matching between different machines is expected to play a critical role to the success of EUV. This work seeks to further the study by quantifying the simulated edge placement error on realistic 7 nm / 5 nm node designs resulting from a fleet consisting of multiple EUV tools, under the assumption of single OPC model / mask for multiple tools and whether such assumptions are valid. Given the importance of tool-to-tool aberration matching in EUVL, this study investigates the amount of variation in tool-to-tool aberration that can be tolerated before foundries must consider tool dedicated OPC mask sets. This study statistically analyzes different metrics such as EPEs, image shifts and worst case excursions to understand which single tool in the fleet should be best used in model calibration to generate the OPC mask shapes. In addition, an effort to rank relative quality of the verification solutions is investigated, to be used to tool allocation.
Chemo, and grapho epitaxy of lines and space structures are now routinely inspected at full wafer level to understand the defectivity limits of the materials and their maximum resolution. In the same manner, there is a deeper understanding about the formation of cylinders using grapho-epitaxy processes. Academia has also contributed by developing methods that help reduce the number of masks in advanced nodes by “combining” DSA-compatible groups, thus reducing the total cost of the process.
From the point of view of EDA, new tools are required when a technology is adopted, and most technologies are adopted when they show a clear cost-benefit over alternative techniques. In addition, years of EDA development have led to the creation of very flexible toolkits that permit rapid prototyping and evaluation of new process alternatives. With the development of high-chi materials, and by moving away of the well characterized PS-PMMA systems, as well as novel integrations in the substrates that work in tandem with diblock copolymer systems, it is necessary to assess any new requirements that may or may not need custom tools to support such processes.
Hybrid DSA processes (which contain both chemo and grapho elements), are currently being investigated as possible contenders for sub-5nm process techniques. Because such processes permit the re-distribution of discontinuities in the regular arrays between the substrate and a cut operation, they have the potential to extend the number of applications for DSA.
This paper illustrates the reason as to why some DSA processes can be supported by existing rules and technology, while other processes require the development of highly customized correction tools and models. It also illustrates how developing DSA cannot be done in isolation, and it requires the full collaboration of EDA, Material’s suppliers, Manufacturing equipment, Metrology, and electronic manufacturers.
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